Advances in Very Large Scale Integration (VLSI) and Ultra Large Scale Integration (ULSI) semiconductor technology have resulted in improvements in the speed and performance of commercially available semiconductor integrated circuit (IC) devices or chips. These advances have increased requirements on packaging technologies used to interconnect such high-performance chips in assembled electronic systems. High-density interconnection of the chips, in conjunction with efficient heat extraction and repairability in a compact structure are among the features needed in modern high-performance chip packaging arrangements.
Previously, high-performance semiconductor devices have been assembled individually in single-chip packages such as pin grid arrays (PGA). The packaged devices are mounted on a printed wiring board (PWB), usually with heat sinks attached to dissipate the heat produced by the devices. However, the long wiring lengths needed to interconnect the devices increase stray capacitances and added inductances, resulting in decreased system performance, while the use of bulky heat sinks increase system size.
More recently, attempts have been made to develop new designs, materials and processes capable of providing high-density multilayer modules with controlled electrical characteristics. One such attempt involves the mounting of bare semiconductor chips on a high-density interconnection substrate using a tape automated bonding (TAB) technique. The bare chip is placed on its back side, that is, the side of the chip opposite the bonding pads, and affixed to a metallized base plate layer of the substrate. The exposed bonding pads of the chip are then bonded to conductors on the substrate by means of known inner lead bonding (ILB) and outer lead bonding (OLB) TAB techniques.
In this arrangement, the "pitch" of the TAB packaging leads is greater than the pitch of the chip's bonding pads, necessitating a larger bonding area or "footprint" on the substrate. This decreases the packing density of chips on the interconnection substrate. Also, a combined thermal and mechanical process, including vibration equipment, is needed to remove faulty chips.
Another approach to high-density multilayer modules with controlled electrical characteristics is described in an article entitled, "Multi-chip Single Package 32 bit Floating Point Digital Signal Processor With Built-in 64 K-Byte SRAM Cache Memory" by Lin-Hendel et al. in "Proceedings of 39th Electronic Components Conference", May, 1989 at pages 636-640. The article discloses a digital signal processing (DSP) IC and several optimized memory ICs integrated on a high-density, low parasitic silicon substrate to produce a single chip-like processing element module. The IC chips are "solder bumped" and "flip-chip" attached to the substrate. Heat generated by the DSP device is conducted to the substrate structure through the intervening solder bumps and a thin air gap.
One area of concern associated with the use of solder bump bonding involves the possibility of thermal mismatch and subsequent damage to the solder bumps when the semiconductor chips and the substrate are made of dissimilar materials and thus undergo differential thermal expansion and contraction. The resulting high shear strains may fracture the solder bump joints.
A problem also arises when a chip on the high-density substrate fails and must be replaced. If the entire substrate is globally heated during the repair process, degradation in the surface tension of the solder may cause it to flow between the closely-spaced solder bumps, causing short circuits and disrupting the alignment between the chips and substrate bonding pads.
Therefore, an object of the present invention is to provide an improved method and apparatus for high-density semiconductor packaging having high performance off-chip interconnections.
Additionally, an object of the present invention is to provide a compact, high-density chip packaging arrangement having a built-in heat extraction mechanism to remove heat from the mounted, high-performance chips.
In accordance with another aspect of the present invention, an object is to provide a high-density semiconductor packaging technique that facilitates fast, efficient and cost effective replacement of faulty chips without disturbing adjacent devices.